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--Descripción:
--	Este fichero ha sido generado automáticamente por la aplicación Nessy2.0
--	Se trata de un fichero que se llamara user_logic y que estara situado en la carpeta pcores/adaptador_circuito
--
--
--Especificaciones:
--	Circuito a ejecutar:
--		Num. Entradas: 11
--		Num. Salidas: 8
--Autores:
--	Rubén Tarancón Garijo
--	Felipe Serrano Santos
--	Facultad de Informatica. Universidad Complutense de Madrid
--Fecha: 
--	Sun Dec 26 16:55:44 CET 2010
--------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;



entity user_logic is
generic(
	C_SLV_DWIDTH                   : integer              := 32;
	C_NUM_REG                      : integer              := 2
);
port(

	dato_listo					   : out std_logic;
	salida_circuito				   : in std_logic_vector(0 to 31);
	entrada_circuito			   : out std_logic_vector(0 to 31);
	
	Bus2IP_Clk                     : in  std_logic;
	Bus2IP_Reset                   : in  std_logic;
	Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
	Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
	Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
	Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
	IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
	IP2Bus_RdAck                   : out std_logic;
	IP2Bus_WrAck                   : out std_logic;
	IP2Bus_Error                   : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
attribute SIGIS of Bus2IP_Reset  : signal is "RST";
end entity user_logic;


architecture IMP of user_logic is


	signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg1                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_reg_write_sel              : std_logic_vector(0 to 1);
	signal slv_reg_read_sel               : std_logic_vector(0 to 1);
	signal slv_ip2bus_data                : std_logic_vector(0 to C_SLV_DWIDTH-1);
	signal slv_read_ack                   : std_logic;
	signal slv_write_ack                  : std_logic;

	----------------- SEÑALES DEL CIRCUITO -----------------------
	type estado is (E0,E1,E2,E3);
	signal est, sig_est          : estado := E0;
	signal entrada_lista         : std_logic;
	signal senal_clk             : std_logic;
	signal senal_entrada_lista      : std_logic_vector(0 to 3);
	--------------------------------------------------------------

begin


	slv_reg_write_sel <= Bus2IP_WrCE(0 to 1);
	slv_reg_read_sel  <= Bus2IP_RdCE(0 to 1);
	slv_write_ack     <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
	slv_read_ack      <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
	IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
	IP2Bus_WrAck <= slv_write_ack;
	IP2Bus_RdAck <= slv_read_ack;
	IP2Bus_Error <= '0';


	SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
		begin
			if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
				if Bus2IP_Reset = '1' then
					slv_reg0 <= (others => '0');
					entrada_lista <= '0';
					senal_entrada_lista <= "0000";
				else
					case slv_reg_write_sel is
						when "10" =>
							for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
								if ( Bus2IP_BE(byte_index) = '1' ) then
									slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
									senal_entrada_lista(byte_index) <= '1';
								end if;
							end loop;
						when "01" =>
						when others => null;
					end case;
				end if;
				if senal_entrada_lista = "1111" then
					entrada_lista <= '1';
					senal_entrada_lista <= "0000";
				end if;
				if entrada_lista = '1' then
					entrada_lista <= '0';
				end if;
			end if;
	end process SLAVE_REG_WRITE_PROC;


	SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is
		begin
			case slv_reg_read_sel is
				when "10" => slv_ip2bus_data <= slv_reg0;
				when "01" => slv_ip2bus_data <= slv_reg1;
				when others => slv_ip2bus_data <= (others => '0');
			end case;
	end process SLAVE_REG_READ_PROC;


	----------------- MAQUINA DE ESTADOS ----------------------
	SINCRONO: process(Bus2IP_Clk,Bus2IP_Reset)
		begin
			if Bus2IP_Reset = '1' then
				est <= E0;
			elsif Bus2IP_Clk'event and Bus2IP_Clk = '1' then
				est <= sig_est;
			end if;
	end process SINCRONO;


	COMB: process(entrada_lista,senal_clk)
		begin
			sig_est <= est;
			case est is
				when E0 =>
					senal_clk <= '0';
					if entrada_lista = '1' then
						sig_est <= E1;
					end if;
				when E1 =>
					senal_clk <= '0';
					sig_est <= E2;
				when E2 =>
					senal_clk <= '0';
					sig_est <= E3;
				when E3 =>
					senal_clk <= '1';
					sig_est <= E0;
			end case;
	end process COMB;
	
	
	process(Bus2IP_Clk)
	begin
		if Bus2IP_Clk'event and Bus2IP_Clk ='1' then
			slv_reg1 <= salida_circuito;
		end if;
	end process;
	
	dato_listo <= senal_clk;
	entrada_circuito <= slv_reg0;


end IMP;

